Front End
2 days
You need to have experience with or already have knowledge of Logic Design
Identify how data flows from the FPGA System Planner (FSP) to the schematic and PCB
Create a design in FSP
Define the protocols and interfaces in an FSP design
Synthesize the connections in FSP protocols and interfaces
Add terminations and external ports in an FSP design
Generate an Allegro Design Entry HDL schematic from your FSP design
Export your FSP placement to the PCB Editor
Backannotate pin swaps and design changes from the schematic and PCB Editor to FSP
Day 1
Day 2