Relevant Allegro PCB Designer High Speed Option and Allegro Design Entry HDL
This Engineer Explorer course is designed around advanced topics and exploration of the software. This course does not cover basic operations. If you are not actively using the software, then you need to complete the Allegro® PCB Editor, the Allegro Package Designer, or the Allegro Design Entry HDL Front-to-Back Flow course.
In this course, you apply and verify high-speed constraints across a design process. You learn to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, and match the propagation delay of driver
and receiver pairs.
You must have experience with or knowledge of Allegro PCB Editor, Allegro Package Designer, or Allegro Design Entry software.
After completing this course, you will be able to:
Define specific net scheduling of high-speed nets
Match the propagation delay of nets and connections
Define minimum and maximum propagation delays for nets and connections
Identify high-speed constraint violations
Identify all the high-speed constraints that you can apply to the nets in your designs
Create spacing and physical constraints as well as area constraints and class-to-class rules
Create formula-based constraints
Create customized constraints using the SKILL® programming language